Pol Henarejos
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363ad1c9e2
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No need to call distinguished functions on core0/core1.
Signed-off-by: Pol Henarejos <pol.henarejos@cttc.es>
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2022-12-24 01:38:38 +01:00 |
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Pol Henarejos
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bfc82d5de4
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Reset must be confirmed always.
Signed-off-by: Pol Henarejos <pol.henarejos@cttc.es>
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2022-09-23 18:07:05 +02:00 |
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Pol Henarejos
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cd66e65b9c
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Adding ENABLE_POWER_RESET to enable power cycle for reset command. Enabled by default.
Signed-off-by: Pol Henarejos <pol.henarejos@cttc.es>
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2022-09-23 16:46:16 +02:00 |
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Pol Henarejos
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2d496fd8fc
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Random functions shall be called for each core, otherwise it will hung.
Signed-off-by: Pol Henarejos <pol.henarejos@cttc.es>
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2022-09-22 20:18:05 +02:00 |
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Pol Henarejos
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d95bc1aba6
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Reset shall call for user presence and can only be called within the 10 seconds from boot.
Signed-off-by: Pol Henarejos <pol.henarejos@cttc.es>
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2022-09-22 19:25:04 +02:00 |
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Pol Henarejos
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a3c60f762d
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Reorganizing core0/core1 split.
Now CBOR and APDU (i.e., intensive processing) areas are executed on core1, while core0 is dedicated for hardware tasks (usb, button, led, etc.).
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2022-09-20 14:39:59 +02:00 |
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Pol Henarejos
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24f48e33bb
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Reset nows flushes the memory storage.
Signed-off-by: Pol Henarejos <pol.henarejos@cttc.es>
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2022-09-19 17:20:00 +02:00 |
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Pol Henarejos
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3873303309
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Refactor CTAP2 file structure.
Signed-off-by: Pol Henarejos <pol.henarejos@cttc.es>
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2022-09-15 14:16:12 +02:00 |
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