Pol Henarejos
badb1780c6
Added read procedures to take values from the cache.
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Fixed lockcout bug.
Added wait_to_finish procedure, which blocks until all cache is written into the ram.
Signed-off-by: Pol Henarejos <pol.henarejos@cttc.es >
2022-02-07 11:13:13 +01:00
Pol Henarejos
30a517908c
Rewrite flash from scratch. We are migrating to a file system approach.
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Signed-off-by: Pol Henarejos <pol.henarejos@cttc.es >
2022-02-05 01:31:24 +01:00
Pol Henarejos
fcfe24b089
Fix erase sector.
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Signed-off-by: Pol Henarejos <pol.henarejos@cttc.es >
2022-01-24 18:04:56 +01:00
Pol Henarejos
9777219ebb
The other core needs to be paused. This is funny because it is not documented in anywhere. Lots of hours spent on this.
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Signed-off-by: Pol Henarejos <pol.henarejos@cttc.es >
2022-01-19 00:55:45 +01:00
Pol Henarejos
189c095f1f
Flash procedures shall be called from core 0.
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We created an exclusive mechanism to share cached pages to write onto flash.
Signed-off-by: Pol Henarejos <pol.henarejos@cttc.es >
2022-01-18 00:17:43 +01:00
Pol Henarejos
0af5685495
Adding the rest of files:
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- ASM is disabled
- Neug needs full rewrite
- Flash is based on PiMoroni 4MB flash (needs adjust)
Signed-off-by: Pol Henarejos <pol.henarejos@cttc.es >
2022-01-03 02:02:39 +01:00
