Squashed 'vendor/ruvector/' content from commit b64c2172
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examples/ultra-low-latency-sim/src/lib.rs
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151
examples/ultra-low-latency-sim/src/lib.rs
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//! Ultra-Low-Latency Meta-Simulation Library
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//!
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//! Core primitives for achieving quadrillion-scale simulations per second
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//! through meta-simulation techniques on CPU with SIMD.
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//!
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//! # Meta-Simulation Techniques
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//!
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//! ## 1. Bit-Parallel Simulation
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//! Each `u64` word represents 64 binary states evolved simultaneously.
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//! Perfect for: Cellular automata, binary Markov chains, boolean networks.
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//!
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//! ## 2. Closed-Form Acceleration
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//! Replace N simulation iterations with analytical solutions.
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//! Perfect for: Ergodic Markov chains, random walks, diffusion processes.
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//!
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//! ## 3. Hierarchical Batching
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//! Each operation represents exponentially many sub-simulations.
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//! Perfect for: Monte Carlo integration, particle systems, ensemble methods.
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//!
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//! ## 4. SIMD Vectorization
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//! Process 4-16 independent simulations per CPU instruction.
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//! Perfect for: Random walks, state evolution, parallel samplers.
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//!
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//! # Theoretical Limits
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//!
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//! ```text
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//! Hardware: M3 Ultra = 1.55 TFLOPS theoretical
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//! Bit-parallel: × 64 (u64 operations)
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//! SIMD: × 4-16 (NEON/AVX)
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//! Hierarchical: × 10-1000 (meta-levels)
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//! Combined: 10,000x+ effective multiplier
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//! ```
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#![allow(dead_code)]
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pub mod bit_parallel;
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pub mod closed_form;
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pub mod hierarchical;
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pub mod simd_ops;
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pub mod verify;
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/// Meta-simulation configuration
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#[derive(Clone, Debug)]
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pub struct MetaSimConfig {
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/// Bit-parallel width (typically 64 for u64)
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pub bit_width: usize,
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/// SIMD vector width in floats
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pub simd_width: usize,
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/// Hierarchy level (each level = batch_size^level multiplier)
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pub hierarchy_level: u32,
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/// Batch size for hierarchical compression
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pub batch_size: usize,
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/// Number of parallel threads
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pub num_threads: usize,
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}
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impl Default for MetaSimConfig {
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fn default() -> Self {
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Self {
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bit_width: 64,
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simd_width: detect_simd_width(),
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hierarchy_level: 2,
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batch_size: 64,
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num_threads: num_cpus(),
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}
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}
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}
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/// Detect SIMD width for current platform
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fn detect_simd_width() -> usize {
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#[cfg(target_arch = "x86_64")]
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{
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if is_x86_feature_detected!("avx512f") {
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return 16;
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}
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if is_x86_feature_detected!("avx2") {
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return 8;
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}
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4 // SSE
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}
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#[cfg(target_arch = "aarch64")]
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{
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4 // NEON is 128-bit = 4 floats
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}
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#[cfg(not(any(target_arch = "x86_64", target_arch = "aarch64")))]
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{
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1 // Scalar
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}
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}
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/// Get number of available CPU cores
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fn num_cpus() -> usize {
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std::thread::available_parallelism()
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.map(|p| p.get())
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.unwrap_or(1)
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}
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/// Calculate effective simulation multiplier
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pub fn effective_multiplier(config: &MetaSimConfig) -> u64 {
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let bit_mult = config.bit_width as u64;
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let simd_mult = config.simd_width as u64;
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let hierarchy_mult = (config.batch_size as u64).pow(config.hierarchy_level);
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let thread_mult = config.num_threads as u64;
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bit_mult * simd_mult * hierarchy_mult * thread_mult
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}
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/// Estimate achievable simulations per second
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pub fn estimate_throughput(config: &MetaSimConfig, base_flops: f64) -> f64 {
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let multiplier = effective_multiplier(config) as f64;
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base_flops * multiplier
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}
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#[cfg(test)]
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mod tests {
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use super::*;
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#[test]
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fn test_default_config() {
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let config = MetaSimConfig::default();
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assert!(config.bit_width >= 64);
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assert!(config.simd_width >= 1);
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assert!(config.num_threads >= 1);
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}
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#[test]
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fn test_effective_multiplier() {
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let config = MetaSimConfig {
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bit_width: 64,
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simd_width: 8,
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hierarchy_level: 2,
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batch_size: 64,
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num_threads: 12,
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};
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let mult = effective_multiplier(&config);
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// 64 * 8 * 64^2 * 12 = 25,165,824
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assert_eq!(mult, 64 * 8 * 4096 * 12);
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}
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#[test]
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fn test_throughput_estimate() {
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let config = MetaSimConfig::default();
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let base_flops = 1e12; // 1 TFLOPS
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let throughput = estimate_throughput(&config, base_flops);
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assert!(throughput > base_flops); // Should be multiplied
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}
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}
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